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Update for 16-11-21 12:30

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Tyler Perkins 2021-11-16 12:30:01 -05:00
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1 changed files with 23 additions and 3 deletions
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@ -257,7 +257,8 @@ for bits 7 and 6.
Bit 5 of ADMUX changes the presentation of the ADC result, and when set to one Bit 5 of ADMUX changes the presentation of the ADC result, and when set to one
(1) the value will be left adjusted, otherwise it will be right adjusted. This (1) the value will be left adjusted, otherwise it will be right adjusted. This
change happens instantly, regardless of the actions in the ADC change happens instantly, regardless of the actions in the ADC. This option is
called ADC Left Adjust Result (ADLAR).
Bits 3-0 set which ADC pin will be converted (NOTE these are the pins on PortC Bits 3-0 set which ADC pin will be converted (NOTE these are the pins on PortC
on the Arduino Nano). For values 0 through 7 (binary values in bits 3-0), will on the Arduino Nano). For values 0 through 7 (binary values in bits 3-0), will
@ -278,9 +279,28 @@ trigger. See the trigger selection bits in ADCSRB. Bit 4 is the interrupt flag
for completed ADC conversions. To Enable this interrupt, write a one to Bit 3, for completed ADC conversions. To Enable this interrupt, write a one to Bit 3,
the ADC interrupt enable. Finally, Bits 2-0 are the ADC prescaler bits. These the ADC interrupt enable. Finally, Bits 2-0 are the ADC prescaler bits. These
determine the division factor between the system clock and the input clock to determine the division factor between the system clock and the input clock to
the ADC. Valid values are shown below the ADC. Valid values are shown below.
| Bits (2-0) | Division Factor | | Bits (2-0) | Division Factor |
-------------------------------- --------------------------------
| | | | 000 | 2 |
| 001 | 2 |
| 010 | 4 |
| 011 | 8 |
| 100 | 16 |
| 101 | 32 |
| 110 | 64 |
| 111 | 128 |
ADCSRB is also used to control the ADC, and Bits 2-0 control the ADC auto
trigger source. All of these conversions occour on the rising edge of the
selected source. If ADEN in ADCSRA is set, then the corresponding interrupts
will be called. (NOTE: Free running mode, 0b000, generates no interrupts and
just continously converts input).
The result of the ADC conversion is stored in the ADC Data Register (ADCH:ADCL
0x79[15:8] and 0x78[7:0]). When ADLAR of ADMUX is set low, Bit 9 of the ADC
data register is the most signifigant bit, and Bit 0 is the least. When ADLAR
is high, Bit 15 is the most signifigant, while Bit 6 is the least.