From 1bf25e48d5d8b9067a0f412b0d345cc0ac9de1ed Mon Sep 17 00:00:00 2001 From: Tyler Perkins Date: Wed, 3 Nov 2021 16:00:02 -0400 Subject: [PATCH] Update for 03-11-21 16:00 --- tech/arduino_nano.wiki | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/tech/arduino_nano.wiki b/tech/arduino_nano.wiki index 7d6bd0c..5254c83 100644 --- a/tech/arduino_nano.wiki +++ b/tech/arduino_nano.wiki @@ -75,7 +75,7 @@ Same pattern: === Interrupts === Interrupts are the same as OS typical interrupts, controlled by the Interrupt -lookup table. On this device the ILT is instead a control register. +lookup table. On this device the ILT is instead a control [[registers]]. The External Interrupt Control Regsiter (EICR 0x69) is a register that allows you to set the behaviour of the two built in interrupts. The Behaviour is set via setting @@ -122,8 +122,13 @@ can be used for PWM for motors and the like. The timers are controlled by the General Timer/Counter Control Register (GTCCR 0x43). Bit 7 is the Timer/Counter sync Mode (TSM) and when set, halts the -timers so that they do not increment during configuration. - +timers so that they do not increment during configuration. Once TSM has a zero +wirtten to it, the PSRASY and PSRSYNC bits (bits 1-0 in this register) are +cleared via hardware, and the timers start counting. Bit 0 is the Prescaler +reset, and will reset the Timer/Counter 0 and 1 prescalers when 1 is written to +it. It is important to not that *Timer/Counter1 and 0 share the same prescaler +and a reset of the prescaler will affect both* + The Timer Counter 1 Control Register A (TCCR1A 0x80) is the register for controlling Timer/Counter 1, along with Timer Counter 1 Control Register B (TCCR1B 0x81). The high sets of two bits (bits 7-6 and 5-4), control the @@ -174,7 +179,6 @@ These Interrupts can be turned on/off using the Timer/Counter 1 Interrupt Mask Register (TIMSK1 0x6F). This register acts similary to the EIMSK register. Bit 5 enables Timer/Counter1 Input capture Interrupt (ICIE1), and the corresponsing interrupt is triggerd when the ICF1 flag in TIFR1 is set. - Bits 2-0 enable the interrupts for Matches with Output Compare B, A, and overflow resepectivly. When Bit 2 is set, the corresponding interrupt is triggered only when the OCF1B flags in TIFR1 is set. This same principle