diff --git a/tech/ATMega328P.wiki b/tech/ATMega328P.wiki
index 1e0d958..f42cd74 100644
--- a/tech/ATMega328P.wiki
+++ b/tech/ATMega328P.wiki
@@ -245,7 +245,8 @@ The primary control register is the ADC Multiplexer Selection Register (ADMUX
 0x7C). Bit 7 and 6 select the reference voltage for the ADC. Any updates to
 this register do not take effect till after an ongoing ADC operations has
 completed. The internal voltage reference may not be used if a voltage is
-applied across the AREF pin. Below are valid values for bits 7 and 6
+applied across the AREF pin (Pin 21 on the Nano). Below are valid values 
+for bits 7 and 6.
 
 | Bits (7-6) | Description |
 ----------------------------
@@ -269,4 +270,6 @@ To control the ADC, the ADC control and Status Register A (ADCSRA 0x7A) and ADC
 Control and Status Register B (ADCSRB 0x7B) are used. Bit 7 of ADCSRA (ADC
 Enable or ADEN) enables the ADC when high (1), and disables when low. 
 Setting this bit low during a conversion will stop the conversion. Bit 6 of
-ADCSRA (ADC Start Conversion or ADSC) 
+ADCSRA (ADC Start Conversion or ADSC) will start the ADC. The first conversion
+performed when enabling this (since ADEN was changed), will take 25 cycles
+instead of 13, due to the init that must be done