From 441a51ffb1d8673e5026d6271d1bc60bf45d6f72 Mon Sep 17 00:00:00 2001
From: Tyler Perkins <tperki17@kent.edu>
Date: Tue, 2 Nov 2021 15:30:01 -0400
Subject: [PATCH] Update for 02-11-21 15:30

---
 tech/D-flip-flop.wiki | 20 +++++++++++++++++++-
 tech/registers.wiki   | 13 ++++++++++++-
 2 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/tech/D-flip-flop.wiki b/tech/D-flip-flop.wiki
index 304df79..71f1140 100644
--- a/tech/D-flip-flop.wiki
+++ b/tech/D-flip-flop.wiki
@@ -8,4 +8,22 @@ and has two inputs and two outputs
 * Q (Stored Data) output
 * NOT_Q (Stored Data) output
 
-The D flip flop only changes on the rising edge of the clock.
+The D flip flop only changes on the rising edge of the clock. To create a
+falling edge flip flop, place a not gate before the CLK signal
+
+== Verilog ==
+
+{{{
+module D_flip_flop(D, EN, Q, Q_NOT);
+    output reg Q;
+    output Q_NOT;
+    input D, EN; //data and enable (clk)
+
+    always @(posedge EN) begin
+        Q <= D;
+    end
+    assign Q_NOT = ~Q;
+
+endmodule
+
+  }}}
diff --git a/tech/registers.wiki b/tech/registers.wiki
index 40a803b..a603eea 100644
--- a/tech/registers.wiki
+++ b/tech/registers.wiki
@@ -8,9 +8,20 @@ A register is a group of [[Flip-flop]]s.
 In general _a n-bit register is a group of n-flip-flops_
 
 Registers with combinational gates hold binary info, and the gates can
-determine how info is moved in/out of the register
+determine how info is moved in/out of the register.
 
 == 4 bit register ==
 
 * Group of 4 [[D-flip-flop]]
+* Change on CLK positive edge
+* Has a clear_b signal that sets all registers to zero before the clock
+  operates
 
+How to change only some bits?
+
+* All gates need to change in parallel
+* Sync the registers by directing control via the D-inputs of the flip flops
+* Add a load line, which can toggle if output of flip flop feeds back into D 
+  - By doing this we can keep the state of the flip flop
+
+== 4 bit shift register ==