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Update for 03-11-21 17:00

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Tyler Perkins 2021-11-03 17:00:01 -04:00
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@ -171,7 +171,7 @@ counter clear is done. The counter will overflow when the max 16 bit value
Timer/Counter 1 Register (TCNT1H:TCNT1L 0x85[15:8] and 0x84[7:0], together TCNT1). Timer/Counter 1 Register (TCNT1H:TCNT1L 0x85[15:8] and 0x84[7:0], together TCNT1).
The Output Compare Register 1 A (OCR1AH:OCR1AL 0x89[15:8] and 0x88[0:7], together OCR1A) The Output Compare Register 1 A (OCR1AH:OCR1AL 0x89[15:8] and 0x88[0:7], together OCR1A)
and Output Compare Register 1 B (OCR1BH:OCR1BL 0x8B[15:8 and 0x8A[0:7]], together OCR1B) and Output Compare Register 1 B (OCR1BH:OCR1BL 0x8B[15:8] and 0x8A[0:7], together OCR1B)
contain 16 bit values are contantly compared to the TCNT1 register. A compare operation is contain 16 bit values are contantly compared to the TCNT1 register. A compare operation is
performed, and a match generates an interupt. performed, and a match generates an interupt.