From 7c134d74abb0258f41cafa426e30bd160c43cf7e Mon Sep 17 00:00:00 2001 From: Tyler Perkins Date: Tue, 16 Nov 2021 12:15:01 -0500 Subject: [PATCH] Update for 16-11-21 12:15 --- tech/ATMega328P.wiki | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/tech/ATMega328P.wiki b/tech/ATMega328P.wiki index f42cd74..85b5a9c 100644 --- a/tech/ATMega328P.wiki +++ b/tech/ATMega328P.wiki @@ -272,4 +272,15 @@ Enable or ADEN) enables the ADC when high (1), and disables when low. Setting this bit low during a conversion will stop the conversion. Bit 6 of ADCSRA (ADC Start Conversion or ADSC) will start the ADC. The first conversion performed when enabling this (since ADEN was changed), will take 25 cycles -instead of 13, due to the init that must be done +instead of 13, due to the init that must be done. Bit 5 of ADCSRA enables auto +triggering of the ADC. The conversion will start on the positive edge of a +trigger. See the trigger selection bits in ADCSRB. Bit 4 is the interrupt flag +for completed ADC conversions. To Enable this interrupt, write a one to Bit 3, +the ADC interrupt enable. Finally, Bits 2-0 are the ADC prescaler bits. These +determine the division factor between the system clock and the input clock to +the ADC. Valid values are shown below + +| Bits (2-0) | Division Factor | +-------------------------------- +| | | +