diff --git a/tech/arduino_nano.wiki b/tech/arduino_nano.wiki
index 44c1129..d072609 100644
--- a/tech/arduino_nano.wiki
+++ b/tech/arduino_nano.wiki
@@ -164,6 +164,32 @@ shown below.
 
 NOTE T1 will trigger the clock even if the pin in configured as output.
 
+The mode of the timer is set using the lower two bits (1-0) of TCCR1A and bits
+4-3 of TCCR1B. The two bits in TCCR1A are known as Waveform Generation Mode 11
+(WGM11) and WGM10 for bits 1 and 0 respectivily. Bits 4-3 on TCCR1B are known
+as WGM13 and WGM12 respecitvly. When ordred WGM13 through WGM10, they create a
+4 bit value. The corresponding values and the effects are shown below.
+
+| Mode | Mode of operation | TOP | Update OCR1* at | TOV1 Flag set on |
+-----------------------------------------------------------------------
+| 0  | Normal                           | 0xFFFF | Immediate | MAX    |
+| 1  | PWM, phase correct, 8bit         | 0x00FF | TOP       | BOTTOM |
+| 2  | PWM, phase correct, 9-bit        | 0x01FF | TOP       | BOTTOM |
+| 3  | PWM, phase correct, 10-bit       | 0x03FF | TOP       | BOTTOM |
+| 4  | CTC                              | OCR1A  | Immediate | MAX    |
+| 5  | Fast PWM, 8bit                   | 0x00FF | BOTTOM    | TOP    |
+| 6  | Fast PWM, 9bit                   | 0x01FF | BOTTOM    | TOP    |
+| 7  | Fast PWM, 10bit                  | 0x03FF | BOTTOM    | TOP    |
+| 8  | PWM, phase and frequency correct | ICR1   | BOTTOM    | BOTTOM |
+| 9  | PWM, phase and frequency correct | OCR1A  | BOTTOM    | BOTTOM |
+| 10 | PWM, phase correct               | ICR1   | TOP       | BOTTOM |
+| 11 | PWM, phase correct               | OCR1A  | TOP       | BOTTOM |
+| 12 | CTC                              | ICR1   | Immediate | MAX    |
+| 13 | RESERVED                         |        |           |        |
+| 14 | Fast PWM                         | ICR1   | BOTTOM    | TOP    |
+| 15 | Fast PWM                         | OCR1A  | BOTTOM    | TOP    |
+
+
 While in normal mode the Timer/Counter 1 Register counts up (inremental) and no
 counter clear is done. The counter will overflow when the max 16 bit value
 (0xFFFF) is reached. The registers that contain the counter values are The