From 921348243e66d9e4b215c547624081da67a08464 Mon Sep 17 00:00:00 2001 From: Tyler Perkins Date: Wed, 3 Nov 2021 15:15:01 -0400 Subject: [PATCH] Update for 03-11-21 15:15 --- tech/arduino_nano.wiki | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/tech/arduino_nano.wiki b/tech/arduino_nano.wiki index 7453cdb..a359ccd 100644 --- a/tech/arduino_nano.wiki +++ b/tech/arduino_nano.wiki @@ -107,8 +107,31 @@ Status Register (SREG 0x5F). Bit 7 is the global interrupt enable flag, and must have a one (1) written to it in order for interrupts to occour, regardless of the state of the EIMSK register. +To implement an interrupt in code, see the following C example +{{{ +//enable the interrupts as explained above +ISR(INT0_vect){ + //perform interrupt task +} + }}} + === Clock === The ATMega328P has 3 timers, two 8bit timers and one 16bit timer. These timers -can be used for PWM for motors and the like. +can be used for PWM for motors and the like. + +The Timer Counter 1 Control Register A (TCCR1A 0x80) is the register for +controlling Timer/Counter 1, along with Timer Counter 1 Control Register B +(TCCR1B 0x81). The high sets of two bits (bits 7-6 and 5-4), control the +compare output mode for channel A and B respectivly. These are controlled with +2 bit combinations as shown below. + +| Bits | Description | +---------------------- +| 00 | Normal Port operation, Comp register disconnected | +| 01 | Toggle OC1A/OC1B on compare match | +| 10 | Clear OC1A/OC1B on compare match (set output low) | +| 11 | Set OC1A/OC1B on compare match (set output high) | + +