From 9ad6ecd5fa7a16995067902f8bfffdedc1bc9b66 Mon Sep 17 00:00:00 2001 From: Tyler Perkins Date: Sat, 20 Nov 2021 19:00:01 -0500 Subject: [PATCH] Update for 20-11-21 19:00 --- tech/SPI.wiki | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/tech/SPI.wiki b/tech/SPI.wiki index ebd8e1d..18ca456 100644 --- a/tech/SPI.wiki +++ b/tech/SPI.wiki @@ -29,4 +29,17 @@ back to the master. On the *rising edge* of the clock, each device reads what is currently set on the respective input port. The chip must also have its output set before the rising edge, to ensure that the device will receive the data it intends to -send. All of this only occurs when CS is set low. +send. All of this only occurs when CS is set low. This is known as *mode 0* + +Ther are several other modes. All of the modes are detailed in the table below. + +| Mode | CLK default | Send on | Sample on | +-------------------------------------------- +| 0 | LOW | falling edge | rising edge | +| 1 | LOW | rising edge | falling edge | +| 2 | HIGH | rising edge | falling edge | +| 3 | HIGH | falling edge | rising edge | + + + +