Update for 03-11-21 15:30
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@ -124,7 +124,9 @@ The Timer Counter 1 Control Register A (TCCR1A 0x80) is the register for
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controlling Timer/Counter 1, along with Timer Counter 1 Control Register B
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(TCCR1B 0x81). The high sets of two bits (bits 7-6 and 5-4), control the
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compare output mode for channel A and B respectivly. These are controlled with
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2 bit combinations as shown below.
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2 bit combinations as shown below.
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NOTE These settings only apply to normal mode
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| Bits | Description |
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----------------------
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@ -133,5 +135,34 @@ compare output mode for channel A and B respectivly. These are controlled with
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| 10 | Clear OC1A/OC1B on compare match (set output low) |
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| 11 | Set OC1A/OC1B on compare match (set output high) |
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TCCRB1B also can change the behaviour of the clock. Bit 7 sets the Input
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Capture Noise Canceler (ICNC1). This will eliminate noise on the pin, and
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delay the input caputre by 4 clock cycles. Bit 6 is the Input Capture Edge
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Select 1 (ICES1). (To write about).
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The lower 3 bits (2-0) determine the clock source. The possible vlaues are
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shown below.
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| Bits | Description |
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----------------------
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| 000 | No clock source (off) |
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| 001 | CLK I/O / 1 (no prescale) |
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| 010 | / 8 Prescaler |
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| 011 | / 64 Prescaler |
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| 100 | / 256 Prescaler |
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| 101 | / 1024 Prescaler |
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| 110 | External Clock source on T1 (falling edge) |
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| 111 | External Clock source on T1 (rising edge) |
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NOTE T1 will trigger the clock even if the pin in configured as output.
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While in normal mode the Timer/Counter 1 Register counts up (inremental) and no
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counter clear is done. The counter will overflow when the max 16 bit value
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(0xFFFF) is reached. The registers that contain the counter values are The
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Timer/Counter 1 Register (TCNT1H:TCNT1L 0x85[15:8] and 0x84[7:0], together TCNT1).
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The Output Compare Register 1 A (OCR1AH:OCR1AL 0x89[15:8] and 0x88[0:7], together OCR1A)
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and Output Compare Register 1 B (OCR1BH:OCR1BL 0x8B[15:8 and 0x8A[0:7]], together OCR1B)
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contain 16 bit values are contantly compared to the TCNT1 register. A compare operation is
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performed, and a match generates an interupt.
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