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Update for 03-11-21 15:30

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Tyler Perkins 2021-11-03 15:30:01 -04:00
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commit acdfc2864f
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@ -126,6 +126,8 @@ controlling Timer/Counter 1, along with Timer Counter 1 Control Register B
compare output mode for channel A and B respectivly. These are controlled with
2 bit combinations as shown below.
NOTE These settings only apply to normal mode
| Bits | Description |
----------------------
| 00 | Normal Port operation, Comp register disconnected |
@ -133,5 +135,34 @@ compare output mode for channel A and B respectivly. These are controlled with
| 10 | Clear OC1A/OC1B on compare match (set output low) |
| 11 | Set OC1A/OC1B on compare match (set output high) |
TCCRB1B also can change the behaviour of the clock. Bit 7 sets the Input
Capture Noise Canceler (ICNC1). This will eliminate noise on the pin, and
delay the input caputre by 4 clock cycles. Bit 6 is the Input Capture Edge
Select 1 (ICES1). (To write about).
The lower 3 bits (2-0) determine the clock source. The possible vlaues are
shown below.
| Bits | Description |
----------------------
| 000 | No clock source (off) |
| 001 | CLK I/O / 1 (no prescale) |
| 010 | / 8 Prescaler |
| 011 | / 64 Prescaler |
| 100 | / 256 Prescaler |
| 101 | / 1024 Prescaler |
| 110 | External Clock source on T1 (falling edge) |
| 111 | External Clock source on T1 (rising edge) |
NOTE T1 will trigger the clock even if the pin in configured as output.
While in normal mode the Timer/Counter 1 Register counts up (inremental) and no
counter clear is done. The counter will overflow when the max 16 bit value
(0xFFFF) is reached. The registers that contain the counter values are The
Timer/Counter 1 Register (TCNT1H:TCNT1L 0x85[15:8] and 0x84[7:0], together TCNT1).
The Output Compare Register 1 A (OCR1AH:OCR1AL 0x89[15:8] and 0x88[0:7], together OCR1A)
and Output Compare Register 1 B (OCR1BH:OCR1BL 0x8B[15:8 and 0x8A[0:7]], together OCR1B)
contain 16 bit values are contantly compared to the TCNT1 register. A compare operation is
performed, and a match generates an interupt.