Update for 03-11-21 18:30

This commit is contained in:
Tyler Perkins 2021-11-03 18:30:01 -04:00
parent 5dc9203b35
commit b48244a525

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@ -55,36 +55,6 @@ a pin to one (1) will enable it for output. The three DDR* registers are DDRB,
which allow for input to taken. These registers are read only. The three PIN* which allow for input to taken. These registers are read only. The three PIN*
registers are PINB (0x23), PINC (0x26), and PIND (0x29). registers are PINB (0x23), PINC (0x26), and PIND (0x29).
* PortC
- Port C data regiser
- 0x28
- R/W 8bits
* DDRC
- Port C data direction register
- 0x27
- R/W 8bits
* PINC
- Port C input pints address
- 0x26
- R 8bits
* PortB
- Port B data register
- 0x25
- R/W 8bits
* DDRB
- Port B data direction register
- 0x24
- R/W 8bits
* PINB
- Port B Input pins address
- 0x23
- R 8bit
Same pattern:
* PortD
- 0x2B - 0x29
=== Interrupts === === Interrupts ===
Interrupts are the same as OS typical interrupts, controlled by the Interrupt Interrupts are the same as OS typical interrupts, controlled by the Interrupt