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Update for 16-11-21 12:45

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Tyler Perkins 2021-11-16 12:45:01 -05:00
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@ -298,9 +298,21 @@ selected source. If ADEN in ADCSRA is set, then the corresponding interrupts
will be called. (NOTE: Free running mode, 0b000, generates no interrupts and
just continously converts input).
| Bits (2-0) | Trigger Source |
-------------------------------
| 000 | Free running mode (No interrupts) |
| 001 | Analog Comparator |
| 010 | External Interrupt 0 |
| 011 | Timer/Counter0 compare Match A |
| 100 | Timer/Counter0 overflow |
| 101 | Timer/Counter1 compare Match B |
| 110 | Timer/Counter1 overflow |
| 111 | Timer/Counter1 capture event |
The result of the ADC conversion is stored in the ADC Data Register (ADCH:ADCL
0x79[15:8] and 0x78[7:0]). When ADLAR of ADMUX is set low, Bit 9 of the ADC
data register is the most signifigant bit, and Bit 0 is the least. When ADLAR
is high, Bit 15 is the most signifigant, while Bit 6 is the least.
When running pins in analog mode, the digital input buffer on the pin can also
be disabled (this is ideal to save power).