diff --git a/tech/ATMega328P.wiki b/tech/ATMega328P.wiki
index d9939a4..1d08b00 100644
--- a/tech/ATMega328P.wiki
+++ b/tech/ATMega328P.wiki
@@ -315,4 +315,8 @@ data register is the most signifigant bit, and Bit 0 is the least. When ADLAR
 is high, Bit 15 is the most signifigant, while Bit 6 is the least.
 
 When running pins in analog mode, the digital input buffer on the pin can also
-be disabled (this is ideal to save power).
+be disabled (this is ideal to save power). This is done by modifying the
+Digital Input Disable Register 0 (DIDR0 0x7E). Bits 5-0 correspond to ADC5-0
+pins (A5-A0 on the Nano). ADC7 and ADC6 do not have digital input pins, and
+therefore do not need digital disable bits.
+