From d92c577eaac17472a859cfba9f7e7a8ec0353371 Mon Sep 17 00:00:00 2001 From: Tyler Perkins Date: Tue, 16 Nov 2021 13:45:01 -0500 Subject: [PATCH] Update for 16-11-21 13:45 --- tech/ATMega328P.wiki | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tech/ATMega328P.wiki b/tech/ATMega328P.wiki index d9939a4..1d08b00 100644 --- a/tech/ATMega328P.wiki +++ b/tech/ATMega328P.wiki @@ -315,4 +315,8 @@ data register is the most signifigant bit, and Bit 0 is the least. When ADLAR is high, Bit 15 is the most signifigant, while Bit 6 is the least. When running pins in analog mode, the digital input buffer on the pin can also -be disabled (this is ideal to save power). +be disabled (this is ideal to save power). This is done by modifying the +Digital Input Disable Register 0 (DIDR0 0x7E). Bits 5-0 correspond to ADC5-0 +pins (A5-A0 on the Nano). ADC7 and ADC6 do not have digital input pins, and +therefore do not need digital disable bits. +