Update for 02-11-21 15:45

tech/J-K-Flip-Flop.wiki

@@ -0,0 +1,10 @@
+= J-K-Flip-Flop =
+
+A J-K-Flip-Flop is the simplest type of flip flop.
+
+* J Input sets the flip flop
+* K input resets the flip flop
+* Q and Q_NOT are the stored state
+
+J-K Flip flops are NOT clock aware, and can have issues of flipping constantly
+when built with real circuts

tech/counters.wiki

@@ -0,0 +1,50 @@
+= Counters =
+
+Counters are special [[registers]] that go through a predetermined sequence of
+states upon application of the input pulse.
+
+* Input pulse comes from clock
+* Counters are in two catagories 
+  - Ripple - Flip flop output serves as input for triggering other flip flops
+  - Synchronous - Clock inputs of all flip-flops receive the common clock pulse
+
+== 4 bit binary ripple counter ==
+
+* Flip flops are in series
+* output of each flip-flop connects to the clock input of the next higher order
+  flip-flop
+* The flip with the leas significant bit receives the CLK pulse
+
+=== Verilog ===
+{{{
+module Ripple_Counter_4bit (A3, A2, A1, A0, Count, Reset);
+    output A3, A2, A1, A0;
+    input Count, Reset;
+    // Instantiate complementing flip-flop
+    Comp_D_flip_flop F0 (A0, Count, Reset);
+    Comp_D_flip_flop F1 (A1, A0, Reset);
+    Comp_D_flip_flop F2 (A2, A1, Reset);
+    Comp_D_flip_flop F3 (A3, A2, Reset);
+endmodule
+// Complementing flip-flop with delay
+// Input to D flip-flop = Q'
+module Comp_D_flip_flop (Q, CLK, Reset);
+    output Q;
+    input CLK, Reset;
+    reg Q;
+    always @ (negedge CLK, posedge Reset)
+        if (Reset) Q <= 1'b0;
+        else Q <= #2 ~Q;
+    // intra-assignment delay
+endmodule
+  }}}
+
+== 4 bit synchronous counters ==
+
+* Common clock triggers all flip-flops at the same time, rather than in
+  succession
+* The clock pulses are applied to all inputs of the flip flops
+* Uses a [[J-K-Flip-Flop]]
+* A flip-flop is completemented depending on the value of J and K at the clock
+  edge
+

tech/electronics.wiki

@@ -12,6 +12,7 @@ Both digital and analog components
 * [[buffer|Buffer]]
 * [[Flip-flop]]
 * [[registers|Registers]]
+* [[counters|Counters]]
 
 == Theoretical ==
 

tech/registers.wiki

@@ -25,3 +25,13 @@ How to change only some bits?
   - By doing this we can keep the state of the flip flop
 
 == 4 bit shift register ==
+
+* Register that can shift the binary info held in each cell to its neighbor in
+  a selected direction
+* Implementation 
+  - Cascade of flip flops
+  - Output of a flip flop is connected to the D-input of the flip-flop at its
+    right
+  - Each clock pulse shifts the contents of the register on the bit position to
+    its rights
+  - The serial inputs determins the input into the left most flip-flop