From f3ee2b258d9842a12fe2b70a3409cb4a69d36e0b Mon Sep 17 00:00:00 2001 From: Tyler Perkins Date: Tue, 16 Nov 2021 11:45:01 -0500 Subject: [PATCH] Update for 16-11-21 11:45 --- tech/ATMega328P.wiki | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tech/ATMega328P.wiki b/tech/ATMega328P.wiki index 466aeb8..1e0d958 100644 --- a/tech/ATMega328P.wiki +++ b/tech/ATMega328P.wiki @@ -268,4 +268,5 @@ values are not used To control the ADC, the ADC control and Status Register A (ADCSRA 0x7A) and ADC Control and Status Register B (ADCSRB 0x7B) are used. Bit 7 of ADCSRA (ADC Enable or ADEN) enables the ADC when high (1), and disables when low. -Setting this bit low during a conversion will stop the conversion. +Setting this bit low during a conversion will stop the conversion. Bit 6 of +ADCSRA (ADC Start Conversion or ADSC)