= D-flip-Flop =

A D-flip-flop or data flip flop is a type of flip flop that can store a bit,
and has two inputs and two outputs

* D (data) input
* CLK (Clock) input
* Q (Stored Data) output
* NOT_Q (Stored Data) output

The D flip flop only changes on the rising edge of the clock. To create a
falling edge flip flop, place a not gate before the CLK signal

== Verilog ==

{{{
module D_flip_flop(D, EN, Q, Q_NOT);
    output reg Q;
    output Q_NOT;
    input D, EN; //data and enable (clk)

    always @(posedge EN) begin
        Q <= D;
    end
    assign Q_NOT = ~Q;

endmodule

  }}}