238 lines
10 KiB
Plaintext
238 lines
10 KiB
Plaintext
= Arduino Nano =
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A very small arduino product, better for hobby embedding
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see [[arduino_techniques|Programming Techniques]]
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== Features ==
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* ATMEL AVR ATmega328P microcontroller
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* 8 bit @16Mhz
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* 2Kbytes SRAM
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* 32Kbytes flash
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* 1Kbytes EEPROM
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* Three on board LED's * 20 IO pins
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* 6 PWM and 6 ADC
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== Notes ==
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* WHEN UPLOADING BE SURE TO SET BOARD TO ATMEGA328OLD
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- this is the atmega328old for BOARD_SUB in the makefile
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=== Memory ===
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* AVR instructions are 16 or 32bits wide, therefore the flash is 16K x 16
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* EEPROM has endurance of ~10000 write cycles
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* Program counter is 14 bits wide
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* First 32 memory locations (0x0000 - 0x001F) are registers
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* Next 64 registers are standard IO (0x0020 - 0x005F)
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* Next 160 are extended IO (0x0060 - 0x00FF)
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* Everything else is SRAM (0x0100 - 0x08FF)
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=== IO ===
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* GPIO pins
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* Have a Data Direction Register (DDR)
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- Sets if data should go in or out
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* Is kept up via a [[multiplexer]] to decide which bit
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=== Pins ===
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The ATMega328P can control all of its pins via the use of an abstraction,
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called ports. Each port has registers associated to it, and each pin
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corresponds to a bit in a port register.
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Port D controls pins D0 - 7,
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Port C controls the analog Pins,
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Port B controls pins D8 - 13
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Each port has 3 registers associated with it. Port* is the register that allows
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writing to the pins. These are PortB (0x25), PortC (0x28), and PortD (0x2B).
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The Data Direction Registers (DDR*) determine if the Pin is used for Input or
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Output. When a bit is set to zero (0), the pin will be used for input. Setting
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a pin to one (1) will enable it for output. The three DDR* registers are DDRB,
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(0x24), DDRC (0x27), and DDRD (0x2A). Finally, there are the PIN* registers,
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which allow for input to taken. These registers are read only. The three PIN*
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registers are PINB (0x23), PINC (0x26), and PIND (0x29).
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To help with reading, the above info is in this table.
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| Port | DDR | Port | Pin |
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---------------------------
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| B | 0x24 | 0x25 | 0x23 |
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| C | 0x27 | 0x28 | 0x26 |
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| D | 0x2A | 0x2B | 0x29 |
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=== Interrupts ===
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Interrupts are the same as OS typical interrupts, controlled by the Interrupt
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lookup table. On this device the ILT is instead a control [[registers]]. The
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code an interrupt calls is called an Interrupt Service Routine (ISR).
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The External Interrupt Control Regsiter (EICR 0x69) is a register that allows you to set
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the behaviour of the two built in interrupts. The Behaviour is set via setting
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two bits. Bits 3-2 are for Interrupt 1 on pin D3, and Bits 1-0 are for
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Interrupt 0 on pin D2. Below is a table of the values and their behaviour
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| Bits | Description |
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----------------------
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| 00 | Low level makes an interrupt |
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| 01 | Any logical change makes an interrupt |
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| 10 | Falling edge makes an interrupt |
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| 11 | Rising edge makes an interrupt |
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To enable the interrupt, you must write a one (1) to the appropriate bit in the
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External Interrupt Mask Register (EIMSK 0x3D). Bit 0 set INT0, and Bit 1 sets
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INT1.
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NOTE external activity on the pin, once the EIMSK bit is set, will cause an
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interrupt even if the pin is set as an output pin.
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Once an interrupt is triggered, the External Interrupt Flag Register (EIFR
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0x3C) will have a one (1) written to the corresponding bit for that interrupt.
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The flag is set automatically, and cleared once the interrupt has concluded.
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The flag can be cleared by writing to it manually. Bit0 controlls INT0 and Bit
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1 controlls INT1.
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Finally, for interrupts to be enabled at all, a one (1) must be written to the
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Status Register (SREG 0x5F). Bit 7 is the global interrupt enable flag, and
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must have a one (1) written to it in order for interrupts to occour, regardless
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of the state of the EIMSK register.
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To implement an interrupt in code, see the following C example
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{{{
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//enable the interrupts as explained above
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ISR(INT0_vect){
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//perform interrupt task
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}
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}}}
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=== Clock ===
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The ATMega328P has 3 timers, two 8bit timers and one 16bit timer. These timers
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can be used for PWM for motors and the like.
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The timers are controlled by the General Timer/Counter Control Register (GTCCR
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0x43). Bit 7 is the Timer/Counter sync Mode (TSM) and when set, halts the
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timers so that they do not increment during configuration. Once TSM has a zero
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wirtten to it, the PSRASY and PSRSYNC bits (bits 1-0 in this register) are
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cleared via hardware, and the timers start counting. Bit 0 is the Prescaler
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reset, and will reset the Timer/Counter 0 and 1 prescalers when 1 is written to
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it. It is important to not that *Timer/Counter1 and 0 share the same prescaler
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and a reset of the prescaler will affect both*
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The Timer Counter 1 Control Register A (TCCR1A 0x80) is the register for
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controlling Timer/Counter 1, along with Timer Counter 1 Control Register B
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(TCCR1B 0x81). The high sets of two bits (bits 7-6 and 5-4), control the
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compare output mode for channel A and B respectivly. These are controlled with
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2 bit combinations as shown below.
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NOTE These settings only apply to normal mode, and are on TTCR1A
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| Bits | Description |
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----------------------
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| 00 | Normal Port operation, Comp register disconnected |
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| 01 | Toggle OC1A/OC1B on compare match |
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| 10 | Clear OC1A/OC1B on compare match (set output low) |
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| 11 | Set OC1A/OC1B on compare match (set output high) |
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TCCRB1B also can change the behaviour of the clock. Bit 7 sets the Input
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Capture Noise Canceler (ICNC1). This will eliminate noise on the pin, and
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delay the input caputre by 4 clock cycles. Bit 6 is the Input Capture Edge
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Select 1 (ICES1). (To write about).
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The lower 3 bits (2-0) determine the clock source. The possible vlaues are
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shown below.
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| Bits | Description |
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----------------------
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| 000 | No clock source (off) |
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| 001 | CLK I/O / 1 (no prescale) |
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| 010 | / 8 Prescaler |
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| 011 | / 64 Prescaler |
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| 100 | / 256 Prescaler |
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| 101 | / 1024 Prescaler |
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| 110 | External Clock source on T1 (falling edge) |
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| 111 | External Clock source on T1 (rising edge) |
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NOTE T1 will trigger the clock even if the pin in configured as output.
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The mode of the timer is set using the lower two bits (1-0) of TCCR1A and bits
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4-3 of TCCR1B. The two bits in TCCR1A are known as Waveform Generation Mode 11
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(WGM11) and WGM10 for bits 1 and 0 respectivily. Bits 4-3 on TCCR1B are known
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as WGM13 and WGM12 respecitvly. When ordred WGM13 through WGM10, they create a
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4 bit value. The corresponding values and the effects are shown below.
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| Mode | Mode of operation | TOP | Update OCR1* at | TOV1 Flag set on |
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-----------------------------------------------------------------------
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| 0 | Normal | 0xFFFF | Immediate | MAX |
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| 1 | PWM, phase correct, 8bit | 0x00FF | TOP | BOTTOM |
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| 2 | PWM, phase correct, 9-bit | 0x01FF | TOP | BOTTOM |
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| 3 | PWM, phase correct, 10-bit | 0x03FF | TOP | BOTTOM |
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| 4 | Clear on compare match | OCR1A | Immediate | MAX |
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| 5 | Fast PWM, 8bit | 0x00FF | BOTTOM | TOP |
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| 6 | Fast PWM, 9bit | 0x01FF | BOTTOM | TOP |
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| 7 | Fast PWM, 10bit | 0x03FF | BOTTOM | TOP |
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| 8 | PWM, phase and frequency correct | ICR1 | BOTTOM | BOTTOM |
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| 9 | PWM, phase and frequency correct | OCR1A | BOTTOM | BOTTOM |
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| 10 | PWM, phase correct | ICR1 | TOP | BOTTOM |
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| 11 | PWM, phase correct | OCR1A | TOP | BOTTOM |
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| 12 | CTC | ICR1 | Immediate | MAX |
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| 13 | RESERVED | | | |
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| 14 | Fast PWM | ICR1 | BOTTOM | TOP |
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| 15 | Fast PWM | OCR1A | BOTTOM | TOP |
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While in normal mode the Timer/Counter 1 Register counts up (inremental) and no
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counter clear is done. The counter will overflow when the max 16 bit value
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(0xFFFF) is reached. The registers that contain the counter values are The
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Timer/Counter 1 Register (TCNT1H:TCNT1L 0x85[15:8] and 0x84[7:0], together TCNT1).
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The Output Compare Register 1 A (OCR1AH:OCR1AL 0x89[15:8] and 0x88[0:7], together OCR1A)
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and Output Compare Register 1 B (OCR1BH:OCR1BL 0x8B[15:8] and 0x8A[0:7], together OCR1B)
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contain 16 bit values are contantly compared to the TCNT1 register. A compare operation is
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performed, and a match generates an interupt.
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These Interrupts can be turned on/off using the Timer/Counter 1 Interrupt Mask
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Register (TIMSK1 0x6F). This register acts similary to the EIMSK register. Bit
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5 enables Timer/Counter1 Input capture Interrupt (ICIE1), and the corresponsing
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interrupt is triggerd when the ICF1 flag in TIFR1 is set.
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Bits 2-0 enable the interrupts for Matches with Output Compare B, A, and
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overflow resepectivly. When Bit 2 is set, the corresponding interrupt is
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triggered only when the OCF1B flags in TIFR1 is set. This same principle
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applies for OCF1A in TIFR1 for Bit 1, and TOV1 in TIFR1 for Bit 0. For more
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info on TIFR1, refer below.
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THe Timer/Counter 1 Interrupt Flag Register (TIFR1 0x36) is the register that holds
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flags when Counter 1 (TCNT1) reaches the values in OCR1A and OCR1B. Bit 5 is
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set when The input capture set by WGM to be used as the TOP value. Bits 2-0 are
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set when TCNT1 matches the value in OCR1B, OCR1A, when when TCNT1 overflows,
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respectivly.
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==== Prescaler ====
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To make the clock useful, the following will be an example of how to use Timer
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1 to delay a certain amount of time. You will need the following information
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* CPU freq (16MHz)
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* Max timer value (0xFFFF or 65536)
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* Chosen Prescaler (See above for prescaler values)
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Divide the CPU freq by the chosen prescaler. Then divide that result through
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the desired freqency. Be sure that the value is smaller than the max timer
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value. If it is to large, choose a larger prescaler. Then place this in the
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OCR** Register and enable the desired interrupt.
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To assist in finding the correct value, below are the values of the clock speed
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(16Mhz) over the prescalers.
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NOTE to help with calculations, 0xFFFF is 65536 and 0xFF is 256
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| prescaler | value |
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---------------------
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| 8 | 2000000 |
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| 64 | 250000 |
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| 256 | 62500 |
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| 1024 | 15625 |
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