30 lines
590 B
Plaintext
30 lines
590 B
Plaintext
= D-flip-Flop =
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A D-flip-flop or data flip flop is a type of flip flop that can store a bit,
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and has two inputs and two outputs
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* D (data) input
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* CLK (Clock) input
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* Q (Stored Data) output
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* NOT_Q (Stored Data) output
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The D flip flop only changes on the rising edge of the clock. To create a
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falling edge flip flop, place a not gate before the CLK signal
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== Verilog ==
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{{{
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module D_flip_flop(D, EN, Q, Q_NOT);
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output reg Q;
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output Q_NOT;
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input D, EN; //data and enable (clk)
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always @(posedge EN) begin
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Q <= D;
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end
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assign Q_NOT = ~Q;
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endmodule
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}}}
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