51 lines
1.5 KiB
Plaintext
51 lines
1.5 KiB
Plaintext
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= Counters =
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Counters are special [[registers]] that go through a predetermined sequence of
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states upon application of the input pulse.
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* Input pulse comes from clock
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* Counters are in two catagories
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- Ripple - Flip flop output serves as input for triggering other flip flops
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- Synchronous - Clock inputs of all flip-flops receive the common clock pulse
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== 4 bit binary ripple counter ==
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* Flip flops are in series
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* output of each flip-flop connects to the clock input of the next higher order
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flip-flop
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* The flip with the leas significant bit receives the CLK pulse
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=== Verilog ===
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{{{
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module Ripple_Counter_4bit (A3, A2, A1, A0, Count, Reset);
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output A3, A2, A1, A0;
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input Count, Reset;
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// Instantiate complementing flip-flop
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Comp_D_flip_flop F0 (A0, Count, Reset);
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Comp_D_flip_flop F1 (A1, A0, Reset);
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Comp_D_flip_flop F2 (A2, A1, Reset);
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Comp_D_flip_flop F3 (A3, A2, Reset);
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endmodule
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// Complementing flip-flop with delay
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// Input to D flip-flop = Q'
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module Comp_D_flip_flop (Q, CLK, Reset);
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output Q;
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input CLK, Reset;
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reg Q;
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always @ (negedge CLK, posedge Reset)
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if (Reset) Q <= 1'b0;
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else Q <= #2 ~Q;
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// intra-assignment delay
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endmodule
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}}}
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== 4 bit synchronous counters ==
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* Common clock triggers all flip-flops at the same time, rather than in
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succession
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* The clock pulses are applied to all inputs of the flip flops
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* Uses a [[J-K-Flip-Flop]]
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* A flip-flop is completemented depending on the value of J and K at the clock
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edge
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