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Update for 03-11-21 15:00

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Tyler Perkins 2021-11-03 15:00:01 -04:00
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@ -102,10 +102,13 @@ The flag is set automatically, and cleared once the interrupt has concluded.
The flag can be cleared by writing to it manually. Bit0 controlls INT0 and Bit
1 controlls INT1.
Finally, for interrupts to be enabled at all, a one (1) must be written to the
Status Register (SREG 0x5F). Bit 7 is the global interrupt enable flag, and
must have a one (1) written to it in order for interrupts to occour, regardless
of the state of the EIMSK register.
=== Clock ===
The ATMega328P has 3 timers, two 8bit timers and one 16bit timer. These timers
can be used for PWM for motors and the like.
[[embedded]]