Update for 03-11-21 14:55
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@ -77,6 +77,30 @@ Same pattern:
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Interrupts are the same as OS typical interrupts, controlled by the Interrupt
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lookup table. On this device the ILT is instead a control register.
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The External Interrupt Control Regsiter (EICR 0x69) is a register that allows you to set
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the behaviour of the two built in interrupts. The Behaviour is set via setting
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two bits. Bits 3-2 are for Interrupt 1 on pin D3, and Bits 1-0 are for
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Interrupt 0 on pin D2. Below is a table of the values and their behaviour
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| Bits | Description |
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----------------------
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| 00 | Low level makes an interrupt |
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| 01 | Any logical change makes an interrupt |
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| 10 | Falling edge makes an interrupt |
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| 11 | Rising edge makes an interrupt |
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To enable the interrupt, you must write a one (1) to the appropriate bit in the
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External Interrupt Mask Register (EIMSK 0x3D). Bit 0 set INT0, and Bit 1 sets
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INT1.
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NOTE external activity on the pin, once the EIMSK bit is set, will cause an
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interrupt even if the pin is set as an output pin.
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Once an interrupt is triggered, the External Interrupt Flag Register (EIFR
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0x3C) will have a one (1) written to the corresponding bit for that interrupt.
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The flag is set automatically, and cleared once the interrupt has concluded.
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The flag can be cleared by writing to it manually. Bit0 controlls INT0 and Bit
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1 controlls INT1.
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=== Clock ===
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