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Update for 03-11-21 14:55

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Tyler Perkins 2021-11-03 14:55:21 -04:00
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@ -77,6 +77,30 @@ Same pattern:
Interrupts are the same as OS typical interrupts, controlled by the Interrupt Interrupts are the same as OS typical interrupts, controlled by the Interrupt
lookup table. On this device the ILT is instead a control register. lookup table. On this device the ILT is instead a control register.
The External Interrupt Control Regsiter (EICR 0x69) is a register that allows you to set
the behaviour of the two built in interrupts. The Behaviour is set via setting
two bits. Bits 3-2 are for Interrupt 1 on pin D3, and Bits 1-0 are for
Interrupt 0 on pin D2. Below is a table of the values and their behaviour
| Bits | Description |
----------------------
| 00 | Low level makes an interrupt |
| 01 | Any logical change makes an interrupt |
| 10 | Falling edge makes an interrupt |
| 11 | Rising edge makes an interrupt |
To enable the interrupt, you must write a one (1) to the appropriate bit in the
External Interrupt Mask Register (EIMSK 0x3D). Bit 0 set INT0, and Bit 1 sets
INT1.
NOTE external activity on the pin, once the EIMSK bit is set, will cause an
interrupt even if the pin is set as an output pin.
Once an interrupt is triggered, the External Interrupt Flag Register (EIFR
0x3C) will have a one (1) written to the corresponding bit for that interrupt.
The flag is set automatically, and cleared once the interrupt has concluded.
The flag can be cleared by writing to it manually. Bit0 controlls INT0 and Bit
1 controlls INT1.
=== Clock === === Clock ===