Update for 03-11-21 17:30
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@ -164,6 +164,32 @@ shown below.
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NOTE T1 will trigger the clock even if the pin in configured as output.
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The mode of the timer is set using the lower two bits (1-0) of TCCR1A and bits
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4-3 of TCCR1B. The two bits in TCCR1A are known as Waveform Generation Mode 11
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(WGM11) and WGM10 for bits 1 and 0 respectivily. Bits 4-3 on TCCR1B are known
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as WGM13 and WGM12 respecitvly. When ordred WGM13 through WGM10, they create a
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4 bit value. The corresponding values and the effects are shown below.
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| Mode | Mode of operation | TOP | Update OCR1* at | TOV1 Flag set on |
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-----------------------------------------------------------------------
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| 0 | Normal | 0xFFFF | Immediate | MAX |
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| 1 | PWM, phase correct, 8bit | 0x00FF | TOP | BOTTOM |
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| 2 | PWM, phase correct, 9-bit | 0x01FF | TOP | BOTTOM |
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| 3 | PWM, phase correct, 10-bit | 0x03FF | TOP | BOTTOM |
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| 4 | CTC | OCR1A | Immediate | MAX |
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| 5 | Fast PWM, 8bit | 0x00FF | BOTTOM | TOP |
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| 6 | Fast PWM, 9bit | 0x01FF | BOTTOM | TOP |
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| 7 | Fast PWM, 10bit | 0x03FF | BOTTOM | TOP |
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| 8 | PWM, phase and frequency correct | ICR1 | BOTTOM | BOTTOM |
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| 9 | PWM, phase and frequency correct | OCR1A | BOTTOM | BOTTOM |
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| 10 | PWM, phase correct | ICR1 | TOP | BOTTOM |
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| 11 | PWM, phase correct | OCR1A | TOP | BOTTOM |
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| 12 | CTC | ICR1 | Immediate | MAX |
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| 13 | RESERVED | | | |
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| 14 | Fast PWM | ICR1 | BOTTOM | TOP |
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| 15 | Fast PWM | OCR1A | BOTTOM | TOP |
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While in normal mode the Timer/Counter 1 Register counts up (inremental) and no
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counter clear is done. The counter will overflow when the max 16 bit value
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(0xFFFF) is reached. The registers that contain the counter values are The
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