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Update for 20-11-21 19:00

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Tyler Perkins 2021-11-20 19:00:01 -05:00
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@ -29,4 +29,17 @@ back to the master.
On the *rising edge* of the clock, each device reads what is currently set on
the respective input port. The chip must also have its output set before the
rising edge, to ensure that the device will receive the data it intends to
send. All of this only occurs when CS is set low.
send. All of this only occurs when CS is set low. This is known as *mode 0*
Ther are several other modes. All of the modes are detailed in the table below.
| Mode | CLK default | Send on | Sample on |
--------------------------------------------
| 0 | LOW | falling edge | rising edge |
| 1 | LOW | rising edge | falling edge |
| 2 | HIGH | rising edge | falling edge |
| 3 | HIGH | falling edge | rising edge |