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Update for 16-11-21 14:00

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Tyler Perkins 2021-11-16 14:00:01 -05:00
parent d92c577eaa
commit cd627b6e24
1 changed files with 11 additions and 7 deletions
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tech/ATMega328P.wiki
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@ -273,13 +273,17 @@ Enable or ADEN) enables the ADC when high (1), and disables when low.
Setting this bit low during a conversion will stop the conversion. Bit 6 of
ADCSRA (ADC Start Conversion or ADSC) will start the ADC. The first conversion
performed when enabling this (since ADEN was changed), will take 25 cycles
instead of 13, due to the init that must be done. Bit 5 of ADCSRA enables auto
triggering of the ADC. The conversion will start on the positive edge of a
trigger. See the trigger selection bits in ADCSRB. Bit 4 is the interrupt flag
for completed ADC conversions. To Enable this interrupt, write a one to Bit 3,
the ADC interrupt enable. Finally, Bits 2-0 are the ADC prescaler bits. These
determine the division factor between the system clock and the input clock to
the ADC. Valid values are shown below.
instead of 13, due to the init that must be done.
Bit 5 of ADCSRA enables auto triggering of the ADC. The conversion will
start on the positive edge of a trigger. See the trigger selection bits in ADCSRB.
Bit 4 is the interrupt flag for completed ADC conversions. To Enable this
interrupt, write a one to Bit 3, the ADC interrupt enable.
Bits 2-0 are the ADC prescaler bits. These determine the division factor
between the system clock and the input clock to the ADC. Valid values are
shown below.
| Bits (2-0) | Division Factor |
--------------------------------