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Update for 03-11-21 15:45

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Tyler Perkins 2021-11-03 15:45:01 -04:00
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@ -120,6 +120,10 @@ ISR(INT0_vect){
The ATMega328P has 3 timers, two 8bit timers and one 16bit timer. These timers
can be used for PWM for motors and the like.
The timers are controlled by the General Timer/Counter Control Register (GTCCR
0x43). Bit 7 is the Timer/Counter sync Mode (TSM) and when set, halts the
timers so that they do not increment during configuration.
The Timer Counter 1 Control Register A (TCCR1A 0x80) is the register for
controlling Timer/Counter 1, along with Timer Counter 1 Control Register B
(TCCR1B 0x81). The high sets of two bits (bits 7-6 and 5-4), control the
@ -166,3 +170,20 @@ and Output Compare Register 1 B (OCR1BH:OCR1BL 0x8B[15:8 and 0x8A[0:7]], togethe
contain 16 bit values are contantly compared to the TCNT1 register. A compare operation is
performed, and a match generates an interupt.
These Interrupts can be turned on/off using the Timer/Counter 1 Interrupt Mask
Register (TIMSK1 0x6F). This register acts similary to the EIMSK register. Bit
5 enables Timer/Counter1 Input capture Interrupt (ICIE1), and the corresponsing
interrupt is triggerd when the ICF1 flag in TIFR1 is set.
Bits 2-0 enable the interrupts for Matches with Output Compare B, A, and
overflow resepectivly. When Bit 2 is set, the corresponding interrupt is
triggered only when the OCF1B flags in TIFR1 is set. This same principle
applies for OCF1A in TIFR1 for Bit 1, and TOV1 in TIFR1 for Bit 0. For more
info on TIFR1, refer below.
THe Timer/Counter 1 Interrupt Flag Register (TIFR1 0x36) is the register that holds
flags when Counter 1 (TCNT1) reaches the values in OCR1A and OCR1B. Bit 5 is
set when The input capture set by WGM to be used as the TOP value. Bits 2-0 are
set when TCNT1 matches the value in OCR1B, OCR1A, when when TCNT1 overflows,
respectivly.