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Update for 03-11-21 16:00

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Tyler Perkins 2021-11-03 16:00:02 -04:00
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tech/arduino_nano.wiki
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@ -75,7 +75,7 @@ Same pattern:
=== Interrupts === === Interrupts ===
Interrupts are the same as OS typical interrupts, controlled by the Interrupt Interrupts are the same as OS typical interrupts, controlled by the Interrupt
lookup table. On this device the ILT is instead a control register. lookup table. On this device the ILT is instead a control [[registers]].
The External Interrupt Control Regsiter (EICR 0x69) is a register that allows you to set The External Interrupt Control Regsiter (EICR 0x69) is a register that allows you to set
the behaviour of the two built in interrupts. The Behaviour is set via setting the behaviour of the two built in interrupts. The Behaviour is set via setting
@ -122,8 +122,13 @@ can be used for PWM for motors and the like.
The timers are controlled by the General Timer/Counter Control Register (GTCCR The timers are controlled by the General Timer/Counter Control Register (GTCCR
0x43). Bit 7 is the Timer/Counter sync Mode (TSM) and when set, halts the 0x43). Bit 7 is the Timer/Counter sync Mode (TSM) and when set, halts the
timers so that they do not increment during configuration. timers so that they do not increment during configuration. Once TSM has a zero
wirtten to it, the PSRASY and PSRSYNC bits (bits 1-0 in this register) are
cleared via hardware, and the timers start counting. Bit 0 is the Prescaler
reset, and will reset the Timer/Counter 0 and 1 prescalers when 1 is written to
it. It is important to not that *Timer/Counter1 and 0 share the same prescaler
and a reset of the prescaler will affect both*
The Timer Counter 1 Control Register A (TCCR1A 0x80) is the register for The Timer Counter 1 Control Register A (TCCR1A 0x80) is the register for
controlling Timer/Counter 1, along with Timer Counter 1 Control Register B controlling Timer/Counter 1, along with Timer Counter 1 Control Register B
(TCCR1B 0x81). The high sets of two bits (bits 7-6 and 5-4), control the (TCCR1B 0x81). The high sets of two bits (bits 7-6 and 5-4), control the
@ -174,7 +179,6 @@ These Interrupts can be turned on/off using the Timer/Counter 1 Interrupt Mask
Register (TIMSK1 0x6F). This register acts similary to the EIMSK register. Bit Register (TIMSK1 0x6F). This register acts similary to the EIMSK register. Bit
5 enables Timer/Counter1 Input capture Interrupt (ICIE1), and the corresponsing 5 enables Timer/Counter1 Input capture Interrupt (ICIE1), and the corresponsing
interrupt is triggerd when the ICF1 flag in TIFR1 is set. interrupt is triggerd when the ICF1 flag in TIFR1 is set.
Bits 2-0 enable the interrupts for Matches with Output Compare B, A, and Bits 2-0 enable the interrupts for Matches with Output Compare B, A, and
overflow resepectivly. When Bit 2 is set, the corresponding interrupt is overflow resepectivly. When Bit 2 is set, the corresponding interrupt is
triggered only when the OCF1B flags in TIFR1 is set. This same principle triggered only when the OCF1B flags in TIFR1 is set. This same principle